This invention relates to the fabrication of metal oxide semiconductor (MOS) integrated circuits (IC's). More particularly, it relates to a process for adding a barrier metal layer over the source and drain areas of MOS IC's. Even more particularly, it relates to a self-aligning process of adding such a barrier metal layer.
When an MOS integrated circuit chip is fabricated, it is one of many chips, arranged in an orderly array on a thin wafer of semiconductor material. The circuit elements, e.g., the sources, drains, gates, metallization, etc., that make up the IC are fabricated in a series of processing steps. Most processing steps require the use of a mask, typically a glass plate which has a pattern of clear and opaque areas. The pattern on the mask defines the area of the wafer that will be subjected to, or protected from, the next processing step.
Prior to a processing step that requires the use of a mask, the wafer is coated with a thin layer of photo sensitive material called a resist. The resist is exposed, by a variety of techniques, with the pattern of the mask. After exposure, the resist is developed in a manner similar to the development of photographic film. The developing process uncovers, or removes, the resist from those areas of the wafer that are to be subjected to the next step of the process, and leaves the resist in place to protect those areas which are not to be subjected to the next step.
When the sources, drains, and gates that make up the elements of the transistors of the IC have been fabricated, a mask is used to add one or more aluminum pads to each of the elements. A layer of insulating glass is then formed over the IC, and a resist/mask step is performed to allow an acid to etch through the glass over the pads, thereby exposing the pads. A mask corresponding to a desired interconnection pattern is then used to form metal traces over the remaining glass to interconnect the transistors via the exposed pads in the desired configuration. More than one layer of metal traces may be used, each separated by a layer of insulating glass.
The alignment of the mask used to perform the various steps described above is very critical. If the mask used in a particular process step is not aligned correctly with respect to previous patterns fabricated, the IC formed may not function correctly, e.g., the resulting IC may not operate fast enough, or it may not function at all.
As the IC technology has progressed to what is now called large scale integration (LSI) and very large scale integration (VLSI), the circuit elements became smaller and more dense. These smaller and more dense circuit elements of LSI and VLSI have significantly added to the alignment problem. Further, as IC technology has improved, the demand for faster circuits has also grown.
In the MOS technology, three important factors can be reduced to increase the speed performance of the circuits. These three factors are: (1) overlap capacitance; (2) contact resistance; and (3) junction depths.
In the prior art, the overlap capacitances between the gate and the source and between the gate and the drain are reduced by an oxide spacer, called a "snowpea" placed along the sides of the gate where it overlaps the source and drain regions. The use and fabrication of this "snowpea" is described more fully hereinafter.
Contact resistance was not a significant factor in increasing circuit speed until such time as the overlap capacitances were reduced. However, with the use of the "snowpea" to reduce capacitance, and with the advent of VLSI technology to produce smaller geometries, contact resistance has increased and has become a dominating factor.
Reducing junction depths is another way known in the art to increase circuit speeds. However, because aluminum migrates a small amount into silicon, great care must be exercised in order to prevent the aluminum pad formed over the source or drain regions from migrating all the way through the source or drain. If such a migration does occur, it causes an electrical short between the metal trace and the semiconductor material in which the source or drain is formed, thereby preventing the transistor from functioning. This is called "junction spiking." Prior to the use of shallow junctions, the junction was thick enough to prevent the aluminum from migrating far enough thereinto to cause junction spiking to occur. Unfortunately, the amount of migration is enough, however, to limit the use of shallow junctions. That is, if the migration is not prevented, the junctions will have to be made deeper than may be desired, and, therefore, the circuits will be slower than desired.
In the prior art, the problem of junction spiking and contact resistance is solved by covering the source and drain areas with a thin layer of a refractory metal, such as nickel, and covering the refractory metal with a layer of aluminum. The refractory metal, called a "barrier metal," does not migrate into the silicon of the source and drain. In addition, aluminum does not migrate into the refractory metal. Thus, the refractory metal acts as a barrier between the aluminum and the shallow junction. The layer of aluminum on the barrier metal replaces the pad previously used. Because of its larger area, it also reduces the contact resistance to an acceptable level.
Disadvantageously, in the prior art, the barrier metal and aluminum are added through the use of resists and masks. If the mask used to add the barrier metal is not in alignment with the source and drain, a portion of the source and drain may not be covered with the barrier metal. When the aluminum is added, the mask used may be slightly out of alignment with respect to the barrier metal. The aluminum can then come in contact with the shallow junction and junction spiking may occur.
One solution to this problem is to make the aluminum area smaller than the barrier metal area. However, doing this may cause the contact resistance to be higher than desired. Moreover, this requires the use of a mask to add the barrier metal, and this is an additional step that adds to the expense of fabricating the IC.
From the above, it is evident that a need exists in the art of MOS IC fabrication for a process or method that can add a barrier metal over the source and drain regions that is self-aligning and that does not require a masking step. Such a process would allow the use of shallow junctions without concern for the hazard of junction spiking.